Digital communication interfaces have become widespread with modern technology's emphasis on rapid transfer and communication of digital data for an ever-increasing amount of important functions, including data storage, output transmission, and device control. These interfaces are used in a number of applications for electronic devices, and include standard communication specifications such as Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), Firewire, etc. USB, for example, is a commonly-used device interface standard that allows data communication between a host and one or more peripheral devices. A link controller (or “link”) is typically used to interface data and signals to and from processors of a system for use with the USB bus. For example, the USB link controller is often embedded in a system on a chip (SoC).
There is increasing demand for smaller products having less cost and power consumption. As smaller deep sub-micron processes are introduced and become widely used, integrating physical layer analog circuitry required by technologies such as USB becomes more challenging. To reduce time-to-market and cost, the link controller SoC can include most of the USB digital logic and a physical layer transceiver (PHY) can be provided in a separate (external) integrated circuit chip which interfaces the link controller with the USB bus.
One standard communication interface used between the USB link controller and the external PHY chip is known as ULPI (UTMI+ Low Pin Interface). This interface is a standard for high-speed USB systems such as USB 2.0 and is an extension of the UTMI+ interface standard (USB Transceiver Macrocell Interface) for managing USB communications. This interface provides data communication of USB packets as well as control signals and a clock signal.
For example, the link controller on the SoC can include a UTMI+ link core and a link wrapper for adapting a large set of UTMI+ signals from the link core to a smaller set of signals used by the ULPI interface and transmitted to the PHY. The PHY chip performs a similar function, having a ULPI wrapper that receives the smaller set of signals from the SoC's link wrapper and adapts and serializes that smaller set of signals to the larger set of UTMI+ signals which can be sent to and processed by a UTMI+ PHY core within the PHY. The PHY core adapts these signals and sends out appropriate signals on the connected USB bus.
The ULPI standard is popular because it allows the number of lines between SoC and PHY to be reduced to 8 or 12 signals by using three control signal lines, a clock line, and eight bi-directional data lines in the widely-used single data rate (SDR) implementation (four bi-directional data lines are specified for double data rate (DDR) implementations). Reducing the number of lines as in the ULPI interface allows a smaller pin count on the PHY and SoC compared to using UTMI, which is advantageous for smaller-scale and higher-frequency integrated circuits since it lowers the cost of integrated circuits and allows a smaller printed circuit board (PCB).
However, despite the reduced pin count allowed by the ULPI interface, the number of pins provided by the ULPI standard can still pose a burden on the use of USB interfaces in today's smaller devices, especially if multiple USB connections are managed simultaneously. Pin count reductions reduce the cost and footprint of the PHY chip on a printed circuit board and reduce the number of pins dedicated to USB for the link controller. Therefore designers and manufacturers of more recent USB devices are interested in ways to reduce this pin count even further.
Some attempts have been made to further reduce the number of pins in the ULPI interface. However, these approaches all have had significant limitations. For example, some approaches require a specialized analog front-end (AFE) rather than the more common CMOS I/O circuits, thus requiring more cost to manufacture. In some approaches, changes are required to the USB software stack, creating further complications in adapting these approaches to the existing standard. In other approaches, a new system PHY is provided (e.g., integrated on chip or package), but this PHY departs significantly from existing hardware and this increases the cost of the system significantly. Interface specifications such as High Speed Inter-Chip (HSIC) and Superspeed Inter-Chip (SSIC) require connections to an entire USB hub core. Thus, these solutions require extensive changes to the standard designs. Furthermore, the long term feasibility of one or more of these approaches may be in question due to rapidly advancing technology threatening to make obsolete such specialized and expensive solutions.
These and other limitations of the prior art will become apparent to those of skill in the art upon a reading of the following descriptions and a study of the several figures of the drawing.